//==================================================================
//--    3段式状态机（Moore型）
//==================================================================


//------------<模块及端口声明>---------------------
module water_led(
	
	input  wire 		clk		,
	input  wire			rst_n	,
	
	output reg [3:0] 	led
   );
	
//------------<reg>---------------------------------
	reg [3:0] 	cur_state;			//定义现态寄存器
	reg [3:0] 	next_state;			//定义次态寄存器
	reg [5:0] 	cnt;

//------------<状态机参数>------
	localparam	led_1 = 4'b0001,
				led_2 = 4'b0010,
				led_3 = 4'b0100,
				led_4 = 4'b1000;
		
//------------<计时模块>--------------------
always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			cnt <= 5'b0;
		else if(cnt == 5'd24)begin  
			cnt <= 5'b0;
			end
		else
			cnt <= cnt + 1'b1;
	end
	
//-------------------------------------------
//--状态机第一段：同步时序，用于描述状态转移
//-------------------------------------------
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		cur_state <= led_1;
	else
		cur_state <= next_state;
end 

//-----------------------------------------------------------
//--状态机第二段：组合逻辑判断状态转移条件，描述状态转移规律
//-----------------------------------------------------------
always@(*)begin
	case(cur_state)
		led_1:begin 
			if(cnt == 5'd5-1 ) 
				next_state=led_2;
			else 
				next_state=led_1;
			end
		led_2:begin 
			if(cnt == 5'd10-1 ) 
				next_state=led_3;
			else 
				next_state=led_2;
			end
		led_3:begin 
			if(cnt == 5'd15-1 ) 
				next_state=led_4;
			else 
				next_state=led_3;
			end
		led_4:begin 
			if(cnt == 5'd20-1 )
				next_state=led_1;
			else 
				next_state=led_4;
			end
		default: next_state=led_1;	
	endcase
end

//---------------------------------
//--状态机第三段：时序逻辑描述输出
//---------------------------------
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		led <= 4'b1111;
	else
		case(cur_state)
			led_1:	led <= 4'b0001;
			led_2:	led <= 4'b0010;
			led_3:	led <= 4'b0100;	
			led_4:	led <= 4'b1000;
			default:led <= 4'b1111;
		endcase
end

endmodule 
